module counter (
  input        clk,
  input        rst_n,
  input        en,
  input [3:0]  load_val,
  input        load,
  output reg [3:0] count
);

always @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    count <= 4'd0;  // 复位时清零
  end else if (load) begin
    count <= load_val;  // 加载值
  end else if (en) begin
    count <= count + 1;  // 计数递增
  end
end

endmodule